Current Mode Multiple-Valued Adder Tree Design for High Performance Arithmetic Applications
نویسندگان
چکیده
Adder trees are the crucial design blocks of many arithmetic VLSI circuits. Alternative implementations can solve the large area requirements and complicated interconnection scheme of these building blocks. Multiple Valued Logic (MVL) implementation of an adder tree can be an alternative design style, which can save from area and interconnect.
منابع مشابه
High Speed Full Swing Current Mode BiCMOS Logical Operators
In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in spee...
متن کاملReducing Hardware Complexity of Wallace Multiplier Using High Order Compressors Based on CNTFET
Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and red...
متن کاملLow-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels
Abstract A new high-speed and low-power threshold detector is proposed to realize high-performance arithmetic VLSI systems. In a conventional threshold detector with a single supply voltage, the input signal swing of a differential-pair circuit (DPC) is too large, which causes large power dissipation together with a long switching delay. The use of two kinds of supply voltages makes the input s...
متن کاملDesign and Simulation of a 2GHz, 64×64 bit Arithmetic Logic Unit in 130nm CMOS Technology
The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In mu...
متن کاملCompact non-binary fast adders using single-electron devices
This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2007